Low power circuits are a desirable feature in many electronic systems, especially those which are portable and thus supplied with a limited supply of power. Previously, CMOS was an attractive alternative to emitter coupled logic (ECL), bipolar and other circuit techniques when power dissipation was an issue. However, with CMOS design features in the sub-micron range and the corresponding increase in switching frequency, power dissipation in CMOS is now a concern. Some recent integrated circuit designs dissipate several tens of watts, which in some cases can stress the packaging technology.
It is known that the amount of energy dissipated during the switching process can be reduced by performing the logic switching at low speeds; this is known as adiabatic switching. Adiabatic switching in this context recycles the signal energy, saves it, and later reuses it to represent other information. Importantly, the slower the circuit is operated, the smaller the amount of energy is dissipated during the switching process. For example, FIG. 6 illustrates a prior art CMOS inverter comprised of a pfet in series with an nfet such that the drains of each device are tied together to the output Y. The nfet is a normally off switch; when there is no charge on the gate, there is no connection between the source and the drain. When charge is placed on the gate, the source is connected to the drain. In contrast, the pfet is a normally on switch; when there is no charge on the gate, there is a connection between the source and the drain. When charge is placed on the gate, the source/drain connection is broken. The load capacitance C represents the gate capacitance of the devices to which the inverter is connected. It can be seen that when X is low, the pfet connect Y to the power supply and isolates it from ground; and when X is high, the nfet connects Y to ground and isolates from the power supply. Thus, this device acts as a logic inverter.
When the output is at voltage V, the capacitor has a charge Q=CV, and is storing a signal energy E=1/2CV.sup.2. Since the power supply had delivered an amount of energy of QV=CV.sup.2, the difference E.sub.h =1/2CV.sup.2 must have been dissipated as heat in the pfet during the charging process. When the input changes back to 1, the load capacitor is discharged to ground, dissipating the signal energy this time in the nfet. Thus, the total energy dissipated in the entire switching loop is CV.sup.2.
Reference is made to FIGS. 7a through 7e. An RC circuit is illustrated in FIG. 7a, in which the resistor R represents an MOS device which has been enabled. Initially, both .beta..sub.1 and V.sub.out are at low potential. .beta..sub.1 applies a step function to the network as shown in FIG. 7b and V.sub.out responds exponentially. At t=0.sup.+, the full voltage is applied across the resistor R. The energy dissipated is E.sub.o =1/2CV.sup.2. If the step is partitioned into two half steps as shown in FIG. 7c, the energy dissipated is E.sub.o =1/4CV.sup.2. Less energy is dissipated in the resistor when the step function of the driving signal is partitioned into smaller step sizes. The final voltage in cases (b) and (c) are the same; however, a longer time period is required for FIG. 7c. In FIG. 7d, the step is further partitioned and in the limit approaches the waveform illustrated in FIG. 7e. The dissipated energy for case (e) is given as (2RC/T)(1/2CV.sup.2). As T is increased larger than an RC time constant, the energy dissipated in the resistor can be decreased significantly.
Thus, it is known in the prior art that the transfer of energy through a dissipative medium can dissipate small amounts of energy if the transfer is made slowly enough. A prior art design called "hot-clock nMOS" applied this principle to MOS circuits, and followed two rules: (1) never disable a switch (MOS device) unless the potential across it is zero; and (2) never enable a switch if there is current flowing through it. By following these rules in the design of MOS circuits, very low power dissipation circuits can be created. In addition, DC to DC converters have also followed these design rules in the prior art.
It is an object of the present invention to provide CMOS logic circuits capable of exhibiting adiabatic-like behavior by employing quasi-static resistive dissipation while providing a reduced device count and optionally providing multiple outputs.